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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-24 11:43:53 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-24 11:43:53 -0500
commit1031b824b975cec999c37cabc8c05c485a4ae5ca (patch)
tree18af5987accd59781642001849908ddb486d069a /src/mem/bus.cc
parent9f07d2ce7ecf435b9a1946f15fb3491bb4636637 (diff)
downloadgem5-1031b824b975cec999c37cabc8c05c485a4ae5ca.tar.xz
MEM: Move port creation to the memory object(s) construction
This patch moves all port creation from the getPort method to be consistently done in the MemObject's constructor. This is possible thanks to the Swig interface passing the length of the vector ports. Previously there was a mix of: 1) creating the ports as members (at object construction time) and using getPort for the name resolution, or 2) dynamically creating the ports in the getPort call. This is now uniform. Furthermore, objects that would not be complete without a port have these ports as members rather than having pointers to dynamically allocated ports. This patch also enables an elaboration-time enumeration of all the ports in the system which can be used to determine the masterId.
Diffstat (limited to 'src/mem/bus.cc')
-rw-r--r--src/mem/bus.cc55
1 files changed, 42 insertions, 13 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index e37449b6e..827adc78e 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -57,6 +57,7 @@ Bus::Bus(const BusParams *p)
: MemObject(p), busId(p->bus_id), clock(p->clock),
headerCycles(p->header_cycles), width(p->width), tickNextIdle(0),
drainEvent(NULL), busIdle(this), inRetry(false),
+ nbrMasterPorts(p->port_master_connection_count),
defaultPortId(INVALID_PORT_ID), useDefaultRange(p->use_default_range),
defaultBlockSize(p->block_size),
cachedBlockSize(0), cachedBlockSizeValid(false)
@@ -68,27 +69,55 @@ Bus::Bus(const BusParams *p)
fatal("Bus clock period must be positive\n");
if (headerCycles <= 0)
fatal("Number of header cycles must be positive\n");
+
+ // create the ports based on the size of the master and slave
+ // vector ports, and the presence of the default master
+
+ // id used to index into interfaces which is a flat vector of all
+ // ports
+ int id = 0;
+ for (int i = 0; i < p->port_master_connection_count; ++i) {
+ std::string portName = csprintf("%s-p%d", name(), id);
+ interfaces.push_back(new BusPort(portName, this, id));
+ ++id;
+ }
+
+ // note that the first slave port is now stored on index
+ // nbrMasterPorts in the vector
+ for (int i = 0; i < p->port_slave_connection_count; ++i) {
+ std::string portName = csprintf("%s-p%d", name(), id);
+ interfaces.push_back(new BusPort(portName, this, id));
+ ++id;
+ }
+
+ // see if we have a default master connected and if so add the
+ // port at the end
+ if (p->port_default_connection_count) {
+ defaultPortId = id;
+ std::string portName = csprintf("%s-default", name());
+ interfaces.push_back(new BusPort(portName, this, id));
+ ++id;
+ }
+
clearPortCache();
}
Port *
Bus::getPort(const std::string &if_name, int idx)
{
- std::string portName;
- int id = interfaces.size();
- if (if_name == "default") {
- if (defaultPortId == INVALID_PORT_ID) {
- defaultPortId = id;
- portName = csprintf("%s-default", name());
- } else
- fatal("Default port already set on %s\n", name());
+ if (if_name == "master") {
+ // the master index translates directly to the interfaces
+ // vector as they are stored first
+ return interfaces[idx];
+ } else if (if_name == "slave") {
+ // the slaves are stored after the masters and we must thus
+ // offset the slave index with the number of master ports
+ return interfaces[nbrMasterPorts + idx];
+ } else if (if_name == "default") {
+ return interfaces[defaultPortId];
} else {
- portName = csprintf("%s-p%d", name(), id);
+ panic("No port %s %d on bus %s\n", if_name, idx, name());
}
- BusPort *bp = new BusPort(portName, this, id);
- interfaces.push_back(bp);
- cachedBlockSizeValid = false;
- return bp;
}
void