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authorAndreas Hansson <andreas.hansson@arm.com>2012-09-21 10:11:24 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-09-21 10:11:24 -0400
commit4aee3aa073f9a20fff88daf0dd224e5c11d84b4e (patch)
tree3bd74d6212cad1ea572fa3a3c355d7ec419b2a9e /src/mem/bus.cc
parent166afc43e0bc2636b6824dd56b59ddbf12ddb4c1 (diff)
downloadgem5-4aee3aa073f9a20fff88daf0dd224e5c11d84b4e.tar.xz
Mem: Tidy up bus member variables types
This patch merely tidies up the types used for the bus member variables. It also makes the constant ones const.
Diffstat (limited to 'src/mem/bus.cc')
-rw-r--r--src/mem/bus.cc10
1 files changed, 1 insertions, 9 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index ba45bfcb5..4dfcbad1c 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -61,15 +61,7 @@ BaseBus::BaseBus(const BaseBusParams *p)
useDefaultRange(p->use_default_range),
defaultBlockSize(p->block_size),
cachedBlockSize(0), cachedBlockSizeValid(false)
-{
- //width, clock period, and header cycles must be positive
- if (width <= 0)
- fatal("Bus width must be positive\n");
- if (clock <= 0)
- fatal("Bus clock period must be positive\n");
- if (headerCycles <= 0)
- fatal("Number of header cycles must be positive\n");
-}
+{}
BaseBus::~BaseBus()
{