Minor fixes for full-system timing memory.

Need to rewrite bus bridge to get any further.

src/dev/io_device.cc:
    Set packet dest on timing responses.
src/mem/bus.cc:
    Fix dest addr bounds check assertion.
    Add assertion to catch infinite loopbacks.
src/mem/physical.cc:
    Add comment.

--HG--
extra : convert_revision : 419b65a3a61e2d099884dbda117b338dffd80896

1 files changed, 2 insertions, 1 deletions

diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index f7c2b874a..e8dfbc2e6 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -54,7 +54,8 @@ Bus::recvTiming(Packet *pkt)
     if (pkt->dest == Packet::Broadcast) {
         port = findPort(pkt->addr, pkt->src);
     } else {
-        assert(pkt->dest > 0 && pkt->dest < interfaces.size());
+        assert(pkt->dest >= 0 && pkt->dest < interfaces.size());
+        assert(pkt->dest != pkt->src); // catch infinite loops
         port = interfaces[pkt->dest];
     }
     return port->sendTiming(pkt);