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author | Anthony Gutierrez <atgutier@umich.edu> | 2012-08-15 10:38:08 -0400 |
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committer | Anthony Gutierrez <atgutier@umich.edu> | 2012-08-15 10:38:08 -0400 |
commit | 0b3897fc90901953e9d016466c37ab507f85023c (patch) | |
tree | 0e8b1fec8d7c4871686903d573e9fd0fd8734d1e /src/mem/bus.cc | |
parent | 5a648f2074caad8aee97e03f27e8eecc527a2cba (diff) | |
download | gem5-0b3897fc90901953e9d016466c37ab507f85023c.tar.xz |
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.
This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
Diffstat (limited to 'src/mem/bus.cc')
-rw-r--r-- | src/mem/bus.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc index ab8b76594..583e60a15 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -52,6 +52,7 @@ #include "base/trace.hh" #include "debug/Bus.hh" #include "debug/BusAddrRanges.hh" +#include "debug/Drain.hh" #include "mem/bus.hh" BaseBus::BaseBus(const BaseBusParams *p) @@ -246,6 +247,7 @@ BaseBus::Layer<PortClass>::releaseLayer() // we see a retry from the destination retryWaiting(); } else if (drainEvent) { + DPRINTF(Drain, "Bus done draining, processing drain event\n"); //If we weren't able to drain before, do it now. drainEvent->process(); // Clear the drain event once we're done with it. @@ -498,6 +500,7 @@ BaseBus::Layer<PortClass>::drain(Event * de) //waiting. We might be idle but have someone waiting if the device we //contacted for a retry didn't actually retry. if (!retryList.empty() || state != IDLE) { + DPRINTF(Drain, "Bus not drained\n"); drainEvent = de; return 1; } |