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| author | Korey Sewell <ksewell@umich.edu> | 2006-07-06 12:18:55 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-07-06 12:18:55 -0400 |
| commit | 03fa13b27ce461886dceef82af0d3e994b5b9288 (patch) | |
| tree | e162c07d55f9fab7f6ad5e29481f9ae2c44f913d /src/mem/bus.cc | |
| parent | 215041215b06f330d072b0537d7fe70739b4927d (diff) | |
| download | gem5-03fa13b27ce461886dceef82af0d3e994b5b9288.tar.xz | |
Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
src/cpu/cpu_models.py:
Use O3DynInst
src/cpu/o3/dyn_inst.hh:
declare O3DynInst here based off of ISA ... this must be updated for each ISA.
src/cpu/static_inst.hh:
take out O3 forward declarations here and include header file to keep this file clean
--HG--
extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0
Diffstat (limited to 'src/mem/bus.cc')
0 files changed, 0 insertions, 0 deletions