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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-08-26 10:14:38 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-08-26 10:14:38 -0400 |
| commit | 9e4cd5bf1ec71023b786b3a779ed4f3ea29ac214 (patch) | |
| tree | d1bbf36638c9c57363bbfdad93c7a541988e66d1 /src/mem/bus.hh | |
| parent | 6fa8015b7fd50e75e97a175a511958b652eca11e (diff) | |
| download | gem5-9e4cd5bf1ec71023b786b3a779ed4f3ea29ac214.tar.xz | |
mem: Fix DRAMSim2 cycle check when restoring from checkpoint
This patch ensures the cycle check is still valid even restoring from
a checkpoint. In this case the DRAMSim2 cycle count is relative to the
startTick rather than 0.
Diffstat (limited to 'src/mem/bus.hh')
0 files changed, 0 insertions, 0 deletions