Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.

src/mem/bus.cc:
src/mem/bus.hh:
    Bus now will be setup with a default responder, unless the user overrides it.  This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
    Bus now has a default responder for FS mode if the user doesn't override it.  It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
    Add bad address device.  Also record when the user has specified their own default responder.

--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85

1 files changed, 7 insertions, 2 deletions

diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 7ec7e6830..619720a79 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -240,6 +240,9 @@ class Bus : public MemObject
     /** Port that handles requests that don't match any of the interfaces.*/
     BusPort *defaultPort;
 
+    /** Has the user specified their own default responder? */
+    bool responderSet;
+
   public:
 
     /** A function used to return the port associated with this bus object. */
@@ -247,9 +250,11 @@ class Bus : public MemObject
 
     virtual void init();
 
-    Bus(const std::string &n, int bus_id, int _clock, int _width)
+    Bus(const std::string &n, int bus_id, int _clock, int _width,
+        bool responder_set)
         : MemObject(n), busId(bus_id), clock(_clock), width(_width),
-        tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL)
+          tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL),
+          responderSet(responder_set)
     {
         //Both the width and clock period must be positive
         if (width <= 0)