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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-06-15 11:45:51 -0400 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-06-15 11:45:51 -0400 |
commit | 88e22ee081f1b0259b624fe320af22a58f144251 (patch) | |
tree | e475bfefa76fa4af2f1c147225c012798193583c /src/mem/bus.hh | |
parent | 185ec39f792386d8b30f3288f2c2e4eaf0b43d02 (diff) | |
download | gem5-88e22ee081f1b0259b624fe320af22a58f144251.tar.xz |
Get Port stuff working with full-system scripts.
Key was adding support for cloning port references (trickier than it sounds).
Got rid of class/instance thing and go back to instance cloning...
still don't allow changing SimObject parameters/children after a
class (instance) has been subclassed or instantiated (or cloned), which
should avoid bizarre unintended behavior.
configs/test/fs.py:
Add ".port" to busses to get a port reference.
Get rid of commented-out code.
src/python/m5/__init__.py:
resolveSimObject should call getCCObject() instead of createCCObject()
to avoid cycles in recursively creating objects.
src/python/m5/config.py:
Get rid of class/instance thing and go back to instance cloning.
Deep copy has to happen only on instance cloning then (and not on subclassing).
Add getCCObject() method to force creation of C++ SimObject without
recursively creating its children.
Add support for cloning port references (trickier than it sounds).
Also clean up some very obsolete comments.
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Device.py:
Add ports.
--HG--
extra : convert_revision : 4816d05ead0de520748aace06dbd1911a33f0af8
Diffstat (limited to 'src/mem/bus.hh')
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