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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:48 -0400 |
| commit | babf072c1c9d37c5324a65fa1a7ef902c4d8fb43 (patch) | |
| tree | 6c297af303dea43c10fee4ac5a5a95548f9b9973 /src/mem/bus.hh | |
| parent | 5c2c3f598ee08875c273e78db7755e1306bea46e (diff) | |
| download | gem5-babf072c1c9d37c5324a65fa1a7ef902c4d8fb43.tar.xz | |
mem: Ensure DRAM refresh respects timings
This patch adds a state machine for the refresh scheduling to
ensure that no accesses are allowed while the refresh is in progress,
and that all banks are propely precharged.
As part of this change, the precharging of banks of broken out into a
method of its own, making is similar to how activations are dealt
with. The idle accounting is also updated to ensure that the refresh
duration is not added to the time that the DRAM is in the idle state
with all banks precharged.
Diffstat (limited to 'src/mem/bus.hh')
0 files changed, 0 insertions, 0 deletions