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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-08-17 05:06:21 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-08-17 05:06:21 -0700
commit0685ae7a2dbceaa2b9b264a57c9d5f82868e777e (patch)
treef640375810c28123381d9f3709793b4db90fcec6 /src/mem/bus.hh
parentc4ba6967a522df3b51a50017d8a5f2c47c382f57 (diff)
downloadgem5-0685ae7a2dbceaa2b9b264a57c9d5f82868e777e.tar.xz
bus: clean up default responder code.
Clean up some minor things left over from the default responder change in rev 9af6fb59752f. Mostly renaming the 'responder_set' param to 'use_default_range' to actually reflect what it does... old name wasn't that descriptive in the first place, but now it really doesn't make sense at all. Also got rid of the bogus obsolete assignment to 'bus.responder' which used to be a parameter but now is interpreted as an implicit child assignment, and which was giving me problems in the config restructuring to come. (A good argument for not allowing implicit child assignments, IMO, but that's water under the bridge, I'm afraid.) Also moved the Bus constructor to the .cc file since that's where it should have been all along.
Diffstat (limited to 'src/mem/bus.hh')
-rw-r--r--src/mem/bus.hh27
1 files changed, 6 insertions, 21 deletions
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 97a65c8a9..ba02e3328 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -305,8 +305,11 @@ class Bus : public MemObject
BusPort *funcPort;
int funcPortId;
- /** Has the user specified their own default responder? */
- bool responderSet;
+ /** If true, use address range provided by default device. Any
+ address not handled by another port and not in default device's
+ range will cause a fatal error. If false, just send all
+ addresses not handled by another port to default device. */
+ bool useDefaultRange;
unsigned defaultBlockSize;
unsigned cachedBlockSize;
@@ -371,25 +374,7 @@ class Bus : public MemObject
unsigned int drain(Event *de);
- Bus(const BusParams *p)
- : MemObject(p), busId(p->bus_id), clock(p->clock),
- headerCycles(p->header_cycles), width(p->width), tickNextIdle(0),
- drainEvent(NULL), busIdle(this), inRetry(false), maxId(0),
- defaultPort(NULL), funcPort(NULL), funcPortId(-4),
- responderSet(p->responder_set), defaultBlockSize(p->block_size),
- cachedBlockSize(0), cachedBlockSizeValid(false)
- {
- //width, clock period, and header cycles must be positive
- if (width <= 0)
- fatal("Bus width must be positive\n");
- if (clock <= 0)
- fatal("Bus clock period must be positive\n");
- if (headerCycles <= 0)
- fatal("Number of header cycles must be positive\n");
- clearBusCache();
- clearPortCache();
- }
-
+ Bus(const BusParams *p);
};
#endif //__MEM_BUS_HH__