DMA: Add IOCache and fix bus bridge to optionally only send requests one

way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964

1 files changed, 2 insertions, 0 deletions

diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 83a4f6a55..0c594c463 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -38,6 +38,7 @@
 #define __MEM_BUS_HH__
 
 #include <string>
+#include <set>
 #include <list>
 #include <inttypes.h>
 
@@ -253,6 +254,7 @@ class Bus : public MemObject
     BusFreeEvent busIdle;
 
     bool inRetry;
+    std::set<int> inRecvStatusChange;
 
     /** max number of bus ids we've handed out so far */
     short maxId;