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authorAli Saidi <saidi@eecs.umich.edu>2007-08-10 16:14:01 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-08-10 16:14:01 -0400
commit06a9f58c68b621f082d39299bdb01f59ef68ef0e (patch)
tree51d9b7982e124d9acccdd8e8fdd8cecf96c0f83f /src/mem/bus.hh
parent5c38668ed68fae7ed18571571d7855b541c4b039 (diff)
downloadgem5-06a9f58c68b621f082d39299bdb01f59ef68ef0e.tar.xz
DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
Diffstat (limited to 'src/mem/bus.hh')
-rw-r--r--src/mem/bus.hh2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 83a4f6a55..0c594c463 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -38,6 +38,7 @@
#define __MEM_BUS_HH__
#include <string>
+#include <set>
#include <list>
#include <inttypes.h>
@@ -253,6 +254,7 @@ class Bus : public MemObject
BusFreeEvent busIdle;
bool inRetry;
+ std::set<int> inRecvStatusChange;
/** max number of bus ids we've handed out so far */
short maxId;