mem: Set the cache line size on a system level

This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.

Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.

A follow-on patch updates the configuration scripts accordingly.

1 files changed, 0 insertions, 11 deletions

diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index fc240a22b..bdcf319f4 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -345,15 +345,6 @@ class BaseBus : public MemObject
     void calcPacketTiming(PacketPtr pkt);
 
     /**
-     * Ask everyone on the bus what their size is and determine the
-     * bus size as either the maximum, or if no device specifies a
-     * block size return the default.
-     *
-     * @return the max of all the sizes or the default if none is set
-     */
-    unsigned deviceBlockSize() const;
-
-    /**
      * Remember for each of the master ports of the bus if we got an
      * address range from the connected slave. For convenience, also
      * keep track of if we got ranges from all the slave modules or
@@ -381,8 +372,6 @@ class BaseBus : public MemObject
        addresses not handled by another port to default device. */
     const bool useDefaultRange;
 
-    uint32_t blockSize;
-
     BaseBus(const BaseBusParams *p);
 
     virtual ~BaseBus();