fix partial writes with a functional memory hack

figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached

configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
    fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
    fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
    by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier

--HG--
extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64

1 files changed, 18 insertions, 4 deletions

diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 0dd7547c5..f0dc67b12 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -133,6 +133,12 @@ class Bus : public MemObject
     /** Occupy the bus with transmitting the packet pkt */
     void occupyBus(PacketPtr pkt);
 
+    /** Ask everyone on the bus what their size is
+     * @param id id of the busport that made the request
+     * @return the max of all the sizes
+     */
+    int findBlockSize(int id);
+
     /** Declaration of the buses port type, one will be instantiated for each
         of the interfaces connecting to the bus. */
     class BusPort : public Port
@@ -195,8 +201,11 @@ class Bus : public MemObject
                                             AddrRangeList &snoop)
         { bus->addressRanges(resp, snoop, id); }
 
-        // Hack to make translating port work without changes
-        virtual int deviceBlockSize() { return 32; }
+        // Ask the bus to ask everyone on the bus what their block size is and
+        // take the max of it. This might need to be changed a bit if we ever
+        // support multiple block sizes.
+        virtual int deviceBlockSize()
+        { return bus->findBlockSize(id); }
 
     };
 
@@ -256,6 +265,10 @@ class Bus : public MemObject
     /** Has the user specified their own default responder? */
     bool responderSet;
 
+    int defaultBlockSize;
+    int cachedBlockSize;
+    bool cachedBlockSizeValid;
+
   public:
 
     /** A function used to return the port associated with this bus object. */
@@ -267,11 +280,12 @@ class Bus : public MemObject
     unsigned int drain(Event *de);
 
     Bus(const std::string &n, int bus_id, int _clock, int _width,
-        bool responder_set)
+        bool responder_set, int dflt_blk_size)
         : MemObject(n), busId(bus_id), clock(_clock), width(_width),
           tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
           maxId(0), defaultPort(NULL), funcPort(NULL), funcPortId(-4),
-          responderSet(responder_set)
+          responderSet(responder_set), defaultBlockSize(dflt_blk_size),
+          cachedBlockSize(0), cachedBlockSizeValid(false)
     {
         //Both the width and clock period must be positive
         if (width <= 0)