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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-06-20 19:04:37 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-06-20 19:04:37 +0000 |
| commit | 0a971cc0c9a6302afb6da5d561b7df24f443eca4 (patch) | |
| tree | 4a56e8a6ee996bdf2381be4cbaf5f7c540d3af8e /src/mem/cache/BaseCache.py | |
| parent | a68ddf685c739220d09fdc44000dd217d0707f8e (diff) | |
| parent | 4a7bc06553577f25e8dc895fa20506c62455a4b6 (diff) | |
| download | gem5-0a971cc0c9a6302afb6da5d561b7df24f443eca4.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : f2fac2b1a09e709021cd8382a9fbe805df2177ef
Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 32f3f0174..55b68f81f 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -90,3 +90,4 @@ class BaseCache(MemObject): "Only prefetch on data not on instruction accesses") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") + addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes") |