diff options
| author | Nathan Binkert <nate@binkert.org> | 2007-08-12 09:56:37 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2007-08-12 09:56:37 -0700 |
| commit | 64295b800fd67e9b9bb3eee0131511a71ddf1fdb (patch) | |
| tree | ed1c759f11384dd2c263b43d7842be2922c5c39d /src/mem/cache/BaseCache.py | |
| parent | b92594dd90f54a892771989a8164148e6647c9ab (diff) | |
| parent | ec4000e0e284834df0eb1db792074a1b11f21cc8 (diff) | |
| download | gem5-64295b800fd67e9b9bb3eee0131511a71ddf1fdb.tar.xz | |
merge
--HG--
extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d
Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 2bf44cdf9..f6d42b1ef 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -81,4 +81,8 @@ class BaseCache(MemObject): "Only prefetch on data not on instruction accesses") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") + cpu_side_filter_ranges = VectorParam.AddrRange([], + "What addresses shouldn't be passed through the side of the bridge") + mem_side_filter_ranges = VectorParam.AddrRange([], + "What addresses shouldn't be passed through the side of the bridge") addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes") |