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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
| commit | 6daf44dae6dbe931e2a1493cd0e33ca9732509dd (patch) | |
| tree | f8815e56c08a92059b5d576728f564c7bfce7bf0 /src/mem/cache/BaseCache.py | |
| parent | c4de6a05229bbc42ae4b247541c823edb8d4ca76 (diff) | |
| parent | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (diff) | |
| download | gem5-6daf44dae6dbe931e2a1493cd0e33ca9732509dd.tar.xz | |
Automated merge with ssh://hg@repo.m5sim.org/m5
Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index dffac2234..5c7ae5274 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -48,6 +48,7 @@ class BaseCache(MemObject): size = Param.MemorySize("capacity in bytes") forward_snoops = Param.Bool(True, "forward snoops from mem side to cpu side") + is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)") subblock_size = Param.Int(0, "Size of subblock in IIC used for compression") tgts_per_mshr = Param.Int("max number of accesses per MSHR") |