diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-10 16:14:01 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-10 16:14:01 -0400 |
| commit | 06a9f58c68b621f082d39299bdb01f59ef68ef0e (patch) | |
| tree | 51d9b7982e124d9acccdd8e8fdd8cecf96c0f83f /src/mem/cache/BaseCache.py | |
| parent | 5c38668ed68fae7ed18571571d7855b541c4b039 (diff) | |
| download | gem5-06a9f58c68b621f082d39299bdb01f59ef68ef0e.tar.xz | |
DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.
--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 2bf44cdf9..f6d42b1ef 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -81,4 +81,8 @@ class BaseCache(MemObject): "Only prefetch on data not on instruction accesses") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") + cpu_side_filter_ranges = VectorParam.AddrRange([], + "What addresses shouldn't be passed through the side of the bridge") + mem_side_filter_ranges = VectorParam.AddrRange([], + "What addresses shouldn't be passed through the side of the bridge") addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes") |