summaryrefslogtreecommitdiff
path: root/src/mem/cache/BaseCache.py
diff options
context:
space:
mode:
authorMrinmoy Ghosh <mrinmoy.ghosh@arm.com>2012-09-25 11:49:41 -0500
committerMrinmoy Ghosh <mrinmoy.ghosh@arm.com>2012-09-25 11:49:41 -0500
commit6fc0094337bc0356c55232c3850fb5fd2dab1f0c (patch)
treef23261eb3f3a7e91b08505e68015941b1d04ba7c /src/mem/cache/BaseCache.py
parent74ab69c7eafc2f0d187ce3ba7d6b9a59ba291b9f (diff)
downloadgem5-6fc0094337bc0356c55232c3850fb5fd2dab1f0c.tar.xz
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets a configurable response latency be set of the cache for the backward path.
Diffstat (limited to 'src/mem/cache/BaseCache.py')
-rw-r--r--src/mem/cache/BaseCache.py4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 081a0f15e..fde0aa492 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -36,7 +36,9 @@ class BaseCache(MemObject):
type = 'BaseCache'
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
- latency = Param.Latency("Latency")
+ hit_latency = Param.Latency("The hit latency for this cache")
+ response_latency = Param.Latency(
+ "Additional cache latency for the return path to core on a miss");
hash_delay = Param.Cycles(1, "time in cycles of hash access")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")