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| author | Dam Sunwoo <dam.sunwoo@arm.com> | 2012-02-12 16:07:39 -0600 |
|---|---|---|
| committer | Dam Sunwoo <dam.sunwoo@arm.com> | 2012-02-12 16:07:39 -0600 |
| commit | 230540e655efd09ad057e7fde2ac257f355c06d1 (patch) | |
| tree | 4555eeff33db9ac5c2f3a1b210627cef4b81d4ad /src/mem/cache/BaseCache.py | |
| parent | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (diff) | |
| download | gem5-230540e655efd09ad057e7fde2ac257f355c06d1.tar.xz | |
mem: fix cache stats to use request ids correctly
This patch fixes the cache stats to use the new request ids.
Cache stats also display the requestor names in the vector subnames.
Most cache stats now include "nozero" and "nonan" flags to reduce the
amount of excessive cache stat dump. Also, simplified
incMissCount()/incHitCount() functions.
Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index e9e60859f..4389eb356 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -27,7 +27,7 @@ # Authors: Nathan Binkert from m5.params import * -from m5.proxy import Self +from m5.proxy import * from MemObject import MemObject from Prefetcher import BasePrefetcher @@ -44,7 +44,6 @@ class BaseCache(MemObject): prioritizeRequests = Param.Bool(False, "always service demand misses first") repl = Param.Repl(NULL, "replacement policy") - num_cpus = Param.Int(1, "number of cpus sharing this cache") size = Param.MemorySize("capacity in bytes") forward_snoops = Param.Bool(True, "forward snoops from mem side to cpu side") @@ -62,3 +61,4 @@ class BaseCache(MemObject): cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port") + system = Param.System(Parent.any, "System we belong to") |