mem: use single BadAddr responder per system.

Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.

1 files changed, 3 insertions, 5 deletions

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index bef1b45d2..bdef07cb4 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -45,6 +45,8 @@ class BaseCache(MemObject):
         "always service demand misses first")
     repl = Param.Repl(NULL, "replacement policy")
     size = Param.MemorySize("capacity in bytes")
+    forward_snoops = Param.Bool(True,
+        "forward snoops from mem side to cpu side")
     subblock_size = Param.Int(0,
         "Size of subblock in IIC used for compression")
     tgts_per_mshr = Param.Int("max number of accesses per MSHR")
@@ -74,8 +76,4 @@ class BaseCache(MemObject):
          "Only prefetch on data not on instruction accesses")
     cpu_side = Port("Port on side closer to CPU")
     mem_side = Port("Port on side closer to MEM")
-    cpu_side_filter_ranges = VectorParam.AddrRange([],
-            "What addresses shouldn't be passed through the side of the bridge")
-    mem_side_filter_ranges = VectorParam.AddrRange([],
-            "What addresses shouldn't be passed through the side of the bridge")
-    addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")
+    addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")