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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-09 09:59:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-09 09:59:25 -0500 |
| commit | eaa994e7f6c12f6dc3e17836052f76a5ce9bdc01 (patch) | |
| tree | d24450f54631a6e82b3c01b93fcf9e698eeee708 /src/mem/cache/BaseCache.py | |
| parent | cda4c2d280e9c1becf3b4d0b6b384f63641c45ba (diff) | |
| download | gem5-eaa994e7f6c12f6dc3e17836052f76a5ce9bdc01.tar.xz | |
cache: Allow main memory to be at disjoint address ranges.
Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index adc48a461..83b3c70c2 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -60,5 +60,5 @@ class BaseCache(MemObject): prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") cpu_side = SlavePort("Port on side closer to CPU") mem_side = MasterPort("Port on side closer to MEM") - addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port") + addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port") system = Param.System(Parent.any, "System we belong to") |