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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-02-05 09:45:20 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-05-31 17:45:23 +0000 |
| commit | 51056cec69a72931a319e7be9370ea63f18e1aa3 (patch) | |
| tree | 9ba8760c4b488879674cfa715ac0b5fff1f4b36c /src/mem/cache/Cache.py | |
| parent | 7d990bd25b478d906442ea63e1de6b381b51817b (diff) | |
| download | gem5-51056cec69a72931a319e7be9370ea63f18e1aa3.tar.xz | |
mem-cache: Add a non-coherent cache
The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.
This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Diffstat (limited to 'src/mem/cache/Cache.py')
| -rw-r--r-- | src/mem/cache/Cache.py | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index a2fa4e90f..230131bdc 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013, 2015 ARM Limited +# Copyright (c) 2012-2013, 2015, 2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -120,3 +120,13 @@ class BaseCache(MemObject): class Cache(BaseCache): type = 'Cache' cxx_header = 'mem/cache/cache.hh' + + +class NoncoherentCache(BaseCache): + type = 'NoncoherentCache' + cxx_header = 'mem/cache/noncoherent_cache.hh' + + # This is typically a last level cache and any clean + # writebacks would be unnecessary traffic to the main memory. + writeback_clean = False + |