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author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-10-10 14:06:00 +0100 |
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committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-10-18 09:40:41 +0000 |
commit | 313c015bbc61da0b8acedc84e4d136835a9f9805 (patch) | |
tree | e9043ea307e6c9027738e53377a23fbec3e906b8 /src/mem/cache/Cache.py | |
parent | bf305c14c47c4bd228c0910ea3bb30ab4bc935e1 (diff) | |
download | gem5-313c015bbc61da0b8acedc84e4d136835a9f9805.tar.xz |
mem: Add write coalescing and write-no-allocate to the caches
Enable the cache to detect contiguous writes and hold on to the MSHR
long enough to allow the entire line to be written. If the whole line
is written, the MSHR will be sent out as an invalidation requests, as
it is part of a whole-line write, i.e. no-fetch-on-write.
The cache is also able to switch to a write-no-allocate policy on the
actual completion of the writes, and instead use the tempBlock and
turn the write operation into a writeback.
These policies are all well-known, and described in works such as
Jouppi, Cache Write Policies and Performance, vol 21, no 2, ACM, 1993.
Change-Id: I19792f2970b3c6798c9b2b493acdd156897284ae
Reviewed-on: https://gem5-review.googlesource.com/c/12907
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache/Cache.py')
-rw-r--r-- | src/mem/cache/Cache.py | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index 230131bdc..8ffab911b 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -41,6 +41,7 @@ from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject from MemObject import MemObject from Prefetcher import BasePrefetcher from ReplacementPolicies import * @@ -51,6 +52,24 @@ from Tags import * # exclusive. class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] +class WriteAllocator(SimObject): + type = 'WriteAllocator' + cxx_header = "mem/cache/cache.hh" + + # Control the limits for when the cache introduces extra delays to + # allow whole-line write coalescing, and eventually switches to a + # write-no-allocate policy. + coalesce_limit = Param.Unsigned(2, "Consecutive lines written before " + "delaying for coalescing") + no_allocate_limit = Param.Unsigned(12, "Consecutive lines written before" + " skipping allocation") + + delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an " + "MSHR with write requests to allow for " + "write coalescing") + + block_size = Param.Int(Parent.cache_line_size, "block size in bytes") + class BaseCache(MemObject): type = 'BaseCache' @@ -116,6 +135,11 @@ class BaseCache(MemObject): clusivity = Param.Clusivity('mostly_incl', "Clusivity with upstream cache") + # The write allocator enables optimizations for streaming write + # accesses by first coalescing writes and then avoiding allocation + # in the current cache. Typically, this would be enabled in the + # data cache. + write_allocator = Param.WriteAllocator(NULL, "Write allocator") class Cache(BaseCache): type = 'Cache' |