diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
| commit | fbdeb6031664d71e19a25f51b6ee882d803dac30 (patch) | |
| tree | 0a3fa9a980e9b9a1013b3aff37080b045192b650 /src/mem/cache/Cache.py | |
| parent | bead7f249a71f8b15ae92b0df9822abb52ca7323 (diff) | |
| download | gem5-fbdeb6031664d71e19a25f51b6ee882d803dac30.tar.xz | |
mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.
The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
Diffstat (limited to 'src/mem/cache/Cache.py')
| -rw-r--r-- | src/mem/cache/Cache.py | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index 531337f19..263b2fea8 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -64,8 +64,6 @@ class BaseCache(MemObject): tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") write_buffers = Param.Unsigned(8, "Number of write buffers") - forward_snoops = Param.Bool(True, - "Forward snoops from mem side to cpu side") is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") |