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authorSteve Reinhardt <Steve.Reinhardt@amd.com>2008-07-16 11:10:33 -0700
committerSteve Reinhardt <Steve.Reinhardt@amd.com>2008-07-16 11:10:33 -0700
commit6629d9b2bc58a885bfebce1517fd12483497b6e4 (patch)
tree22e2bc30405ba483ac571951f49cc77d7e713477 /src/mem/cache/base.cc
parent05d8c9acb8a5a985956998fc13551288496e5cdc (diff)
downloadgem5-6629d9b2bc58a885bfebce1517fd12483497b6e4.tar.xz
mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
Diffstat (limited to 'src/mem/cache/base.cc')
-rw-r--r--src/mem/cache/base.cc9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 956375530..29fa97544 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -41,11 +41,10 @@
using namespace std;
BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
- const std::string &_label,
- std::vector<Range<Addr> > filter_ranges)
+ const std::string &_label)
: SimpleTimingPort(_name, _cache), cache(_cache),
label(_label), otherPort(NULL),
- blocked(false), mustSendRetry(false), filterRanges(filter_ranges)
+ blocked(false), mustSendRetry(false)
{
}
@@ -58,10 +57,12 @@ BaseCache::BaseCache(const Params *p)
blkSize(p->block_size),
hitLatency(p->latency),
numTarget(p->tgts_per_mshr),
+ forwardSnoops(p->forward_snoops),
blocked(0),
noTargetMSHR(NULL),
missCount(p->max_miss_count),
- drainEvent(NULL)
+ drainEvent(NULL),
+ addrRange(p->addr_range)
{
}