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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
| commit | 6daf44dae6dbe931e2a1493cd0e33ca9732509dd (patch) | |
| tree | f8815e56c08a92059b5d576728f564c7bfce7bf0 /src/mem/cache/base.cc | |
| parent | c4de6a05229bbc42ae4b247541c823edb8d4ca76 (diff) | |
| parent | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (diff) | |
| download | gem5-6daf44dae6dbe931e2a1493cd0e33ca9732509dd.tar.xz | |
Automated merge with ssh://hg@repo.m5sim.org/m5
Diffstat (limited to 'src/mem/cache/base.cc')
| -rw-r--r-- | src/mem/cache/base.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 9166e1a09..b7e331d54 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -58,6 +58,7 @@ BaseCache::BaseCache(const Params *p) hitLatency(p->latency), numTarget(p->tgts_per_mshr), forwardSnoops(p->forward_snoops), + isTopLevel(p->is_top_level), blocked(0), noTargetMSHR(NULL), missCount(p->max_miss_count), |