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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-09 04:36:31 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-09 04:36:31 -0400 |
| commit | da4539dc749c3d29c03de9b3130f1c9a7266be9d (patch) | |
| tree | c58cfe7bb1b489f440883cb4ec8a2a25e546aa20 /src/mem/cache/base.cc | |
| parent | 346fe7337009980566e023a60a09391ed893a5c0 (diff) | |
| download | gem5-da4539dc749c3d29c03de9b3130f1c9a7266be9d.tar.xz | |
misc: Fix a number of unitialised variables and members
Static analysis unearther a bunch of uninitialised variables and
members, and this patch addresses the problem. In all cases these
omissions seem benign in the end, but at least fixing them means less
false positives next time round.
Diffstat (limited to 'src/mem/cache/base.cc')
| -rw-r--r-- | src/mem/cache/base.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 70d1b4167..faa000c09 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -67,6 +67,7 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, BaseCache::BaseCache(const Params *p) : MemObject(p), + cpuSidePort(nullptr), memSidePort(nullptr), mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, MSHRQueue_WriteBuffer), @@ -77,6 +78,7 @@ BaseCache::BaseCache(const Params *p) forwardSnoops(p->forward_snoops), isTopLevel(p->is_top_level), blocked(0), + order(0), noTargetMSHR(NULL), missCount(p->max_miss_count), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), |