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| author | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-09-25 11:49:41 -0500 |
|---|---|---|
| committer | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-09-25 11:49:41 -0500 |
| commit | 6fc0094337bc0356c55232c3850fb5fd2dab1f0c (patch) | |
| tree | f23261eb3f3a7e91b08505e68015941b1d04ba7c /src/mem/cache/base.cc | |
| parent | 74ab69c7eafc2f0d187ce3ba7d6b9a59ba291b9f (diff) | |
| download | gem5-6fc0094337bc0356c55232c3850fb5fd2dab1f0c.tar.xz | |
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
Diffstat (limited to 'src/mem/cache/base.cc')
| -rw-r--r-- | src/mem/cache/base.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index c175d5958..4dd428a2e 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -69,7 +69,8 @@ BaseCache::BaseCache(const Params *p) writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, MSHRQueue_WriteBuffer), blkSize(p->block_size), - hitLatency(p->latency), + hitLatency(p->hit_latency), + responseLatency(p->response_latency), numTarget(p->tgts_per_mshr), forwardSnoops(p->forward_snoops), isTopLevel(p->is_top_level), |