mem: Reorganize cache tags and make them a SimObject

This patch reorganizes the cache tags to allow more flexibility to
implement new replacement policies. The base tags class is now a
clocked object so that derived classes can use a clock if they need
one. Also having deriving from SimObject allows specialized Tag
classes to be swapped in/out in .py files.

The cache set is now templatized to allow it to contain customized
cache blocks with additional informaiton. This involved moving code to
the .hh file and removing cacheset.cc.

The statistics belonging to the cache tags are now including ".tags"
in their name. Hence, the stats need an update to reflect the change
in naming.

1 files changed, 13 insertions, 7 deletions

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index ba981b606..62f1bb21b 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -773,13 +773,19 @@ BaseCache::drain(DrainManager *dm)
 BaseCache *
 BaseCacheParams::create()
 {
-    int numSets = size / (assoc * block_size);
-
-    if (numSets == 1) {
-        FALRU *tags = new FALRU(block_size, size, hit_latency);
-        return new Cache<FALRU>(this, tags);
+    unsigned numSets = size / (assoc * block_size);
+
+    assert(tags);
+
+    if (dynamic_cast<FALRU*>(tags)) {
+        if (numSets != 1)
+            fatal("Got FALRU tags with more than one set\n");
+        return new Cache<FALRU>(this);
+    } else if (dynamic_cast<LRU*>(tags)) {
+        if (numSets == 1)
+            warn("Consider using FALRU tags for a fully associative cache\n");
+        return new Cache<LRU>(this);
     } else {
-        LRU *tags = new LRU(numSets, block_size, assoc, hit_latency);
-        return new Cache<LRU>(this, tags);
+        fatal("No suitable tags selected\n");
     }
 }