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authorAndreas Hansson <andreas.hansson@arm.com>2015-08-21 07:03:23 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-08-21 07:03:23 -0400
commitddfa96cf455ba4a287930942514cdf0f7f2afa77 (patch)
tree89eddf6ab0ec6f4660629b45b1b7cff7df6ca82c /src/mem/cache/base.cc
parentd71a0d790d8d1113480c5a57d7bfbb9b7d0d0037 (diff)
downloadgem5-ddfa96cf455ba4a287930942514cdf0f7f2afa77.tar.xz
mem: Add explicit Cache subclass and make BaseCache abstract
Open up for other subclasses to BaseCache and transition to using the explicit Cache subclass. --HG-- rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
Diffstat (limited to 'src/mem/cache/base.cc')
-rw-r--r--src/mem/cache/base.cc12
1 files changed, 2 insertions, 10 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index c270d5b65..41b6f38aa 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -65,13 +65,13 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
{
}
-BaseCache::BaseCache(const Params *p)
+BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
: MemObject(p),
cpuSidePort(nullptr), memSidePort(nullptr),
mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs),
writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0,
MSHRQueue_WriteBuffer),
- blkSize(p->system->cacheLineSize()),
+ blkSize(blk_size),
lookupLatency(p->hit_latency),
forwardLatency(p->hit_latency),
fillLatency(p->response_latency),
@@ -774,11 +774,3 @@ BaseCache::regStats()
;
}
-
-BaseCache *
-BaseCacheParams::create()
-{
- assert(tags);
-
- return new Cache(this);
-}