mem-cache: Add getter and setter to CacheBlk::whenReady

Add a getter and a setter function to access CacheBlk::whenReady
to encapsulate the variable and allow error checking. This error
checking consists on verifying that writes to a block after it
has been inserted follow a chronological order.

As a side effect, tickInserted retain its value until updated,
that is, it is not reset in invalidate().

Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14715
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

1 files changed, 10 insertions, 10 deletions

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 244d7ce4e..bad24f7ee 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -900,10 +900,11 @@ BaseCache::calculateAccessLatency(const CacheBlk* blk,
         }
 
         // Check if the block to be accessed is available. If not, apply the
-        // access latency on top of block->whenReady.
-        if (blk->whenReady > curTick() &&
-            ticksToCycles(blk->whenReady - curTick()) > lat) {
-            lat += ticksToCycles(blk->whenReady - curTick());
+        // access latency on top of when the block is ready to be accessed.
+        const Tick when_ready = blk->getWhenReady();
+        if (when_ready > curTick() &&
+            ticksToCycles(when_ready - curTick()) > lat) {
+            lat += ticksToCycles(when_ready - curTick());
         }
     }
 
@@ -1024,8 +1025,8 @@ BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
         DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
         incHitCount(pkt);
         // populate the time when the block will be ready to access.
-        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
-            pkt->payloadDelay;
+        blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
+            pkt->payloadDelay);
         return true;
     } else if (pkt->cmd == MemCmd::CleanEvict) {
         if (blk) {
@@ -1081,8 +1082,8 @@ BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
 
         incHitCount(pkt);
         // populate the time when the block will be ready to access.
-        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
-            pkt->payloadDelay;
+        blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
+            pkt->payloadDelay);
         // if this a write-through packet it will be sent to cache
         // below
         return !pkt->writeThrough();
@@ -1212,8 +1213,7 @@ BaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
         pkt->writeDataToBlock(blk->data, blkSize);
     }
     // We pay for fillLatency here.
-    blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
-        pkt->payloadDelay;
+    blk->setWhenReady(clockEdge(fillLatency) + pkt->payloadDelay);
 
     return blk;
 }