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| author | Daniel R. Carvalho <odanrc@yahoo.com.br> | 2019-01-30 14:46:22 +0100 |
|---|---|---|
| committer | Daniel Carvalho <odanrc@yahoo.com.br> | 2019-04-19 16:34:00 +0000 |
| commit | 9f32d74db86c8977ab16f2671830f6cdfe3c068b (patch) | |
| tree | b7dd3a867cbe1f7fc29fa68d8173160632523fdf /src/mem/cache/base.cc | |
| parent | f699e91fe53870b6a7f0e9fe61cc92fc44b1033b (diff) | |
| download | gem5-9f32d74db86c8977ab16f2671830f6cdfe3c068b.tar.xz | |
mem-cache: Move Target to QueueEntry
WriteQueueEntry's target has 100% functionality overlap with MSHR's,
therefore make it base to MSHR::Target.
Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache/base.cc')
| -rw-r--r-- | src/mem/cache/base.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 19655a57e..f43c2ecf3 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -439,7 +439,7 @@ BaseCache::recvTimingResp(PacketPtr pkt) } // Initial target is used just for stats - MSHR::Target *initial_tgt = mshr->getTarget(); + QueueEntry::Target *initial_tgt = mshr->getTarget(); int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); Tick miss_latency = curTick() - initial_tgt->recvTime; |