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author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-06-27 12:29:00 -0500 |
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committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-06-27 12:29:00 -0500 |
commit | f6f63ec0aa68f631691d9eccc18739722a0a9f17 (patch) | |
tree | 6d3cd4d0f43381980412ade2ed8266e3d3ba472d /src/mem/cache/base.cc | |
parent | 3be4f4b846f991c98fe1909631996c5b58d52437 (diff) | |
download | gem5-f6f63ec0aa68f631691d9eccc18739722a0a9f17.tar.xz |
mem: write streaming support via WriteInvalidate promotion
Support full-block writes directly rather than requiring RMW:
* a cache line is allocated in the cache upon receipt of a
WriteInvalidateReq, not the WriteInvalidateResp.
* only top-level caches allocate the line; the others just pass
the request along and invalidate as necessary.
* to close a timing window between the *Req and the *Resp, a new
metadata bit tracks whether another cache has read a copy of
the new line before the writeback to memory.
Diffstat (limited to 'src/mem/cache/base.cc')
-rw-r--r-- | src/mem/cache/base.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 2a285bf2f..70d1b4167 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -93,9 +93,9 @@ BaseCache::CacheSlavePort::setBlocked() // if we already scheduled a retry in this cycle, but it has not yet // happened, cancel it if (sendRetryEvent.scheduled()) { - owner.deschedule(sendRetryEvent); - DPRINTF(CachePort, "Cache port %s deschedule retry\n", name()); - mustSendRetry = true; + owner.deschedule(sendRetryEvent); + DPRINTF(CachePort, "Cache port %s deschedule retry\n", name()); + mustSendRetry = true; } } |