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authorAli Saidi <Ali.Saidi@ARM.com>2011-03-17 19:20:19 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-03-17 19:20:19 -0500
commit2f40b3b8ae4fddcdd167fc86469254f40736c888 (patch)
tree4c1e87d403e07d3d8738c65b1d9c50482b94cfde /src/mem/cache/base.hh
parent3a44307e941feb5ec2b2d68ae69c8d1bba3d8437 (diff)
downloadgem5-2f40b3b8ae4fddcdd167fc86469254f40736c888.tar.xz
O3: Fix unaligned stores when cache blocked
Without this change the a store can be issued to the cache multiple times. If this case occurs when the l1 cache is out of mshrs (and thus blocked) the processor will never make forward progress because each cycle it will send a single request using the recently freed mshr and not completing the multipart store. This will continue forever.
Diffstat (limited to 'src/mem/cache/base.hh')
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