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authorAndreas Hansson <andreas.hansson@arm.com>2015-07-30 03:41:43 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-07-30 03:41:43 -0400
commit540e59fd7088fef6cc564babf8c728487b82afd5 (patch)
treece90cac12b6b8087fc5480851138dba13e26e655 /src/mem/cache/base.hh
parent0c89c15b23d4db50eb08f8ebf2a40b569f41dd29 (diff)
downloadgem5-540e59fd7088fef6cc564babf8c728487b82afd5.tar.xz
mem: Remove unused RequestCause in cache
This patch removes the RequestCause, and also simplifies how we schedule the sending of packets through the memory-side port. The deassertion of bus requests is removed as it is not used.
Diffstat (limited to 'src/mem/cache/base.hh')
-rw-r--r--src/mem/cache/base.hh60
1 files changed, 20 insertions, 40 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 041b1f6a5..c3bf6fe87 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -97,16 +97,6 @@ class BaseCache : public MemObject
NUM_BLOCKED_CAUSES
};
- /**
- * Reasons for cache to request a bus.
- */
- enum RequestCause {
- Request_MSHR = MSHRQueue_MSHRs,
- Request_WB = MSHRQueue_WriteBuffer,
- Request_PF,
- NUM_REQUEST_CAUSES
- };
-
protected:
/**
@@ -114,7 +104,7 @@ class BaseCache : public MemObject
* cache, and in addition to the basic timing port that only sends
* response packets through a transmit list, it also offers the
* ability to schedule and send request packets (requests &
- * writebacks). The send event is scheduled through requestBus,
+ * writebacks). The send event is scheduled through schedSendEvent,
* and the sendDeferredPacket of the timing port is modified to
* consider both the transmit list and the requests from the MSHR.
*/
@@ -127,10 +117,9 @@ class BaseCache : public MemObject
* Schedule a send of a request packet (from the MSHR). Note
* that we could already have a retry outstanding.
*/
- void requestBus(RequestCause cause, Tick time)
+ void schedSendEvent(Tick time)
{
- DPRINTF(CachePort, "Scheduling request at %llu due to %d\n",
- time, cause);
+ DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
reqQueue.schedSendEvent(time);
}
@@ -213,7 +202,8 @@ class BaseCache : public MemObject
* - MSHR allocateMissBuffer (miss in MSHR queue);
*/
MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
- PacketPtr pkt, Tick time, bool requestBus)
+ PacketPtr pkt, Tick time,
+ bool sched_send)
{
// check that the address is block aligned since we rely on
// this in a number of places when checking for matches and
@@ -226,9 +216,9 @@ class BaseCache : public MemObject
setBlocked((BlockedCause)mq->index);
}
- if (requestBus) {
- requestMemSideBus((RequestCause)mq->index, time);
- }
+ if (sched_send)
+ // schedule the send
+ schedMemSideSendEvent(time);
return mshr;
}
@@ -510,21 +500,21 @@ class BaseCache : public MemObject
const AddrRangeList &getAddrRanges() const { return addrRanges; }
- MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
+ MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
{
return allocateBufferInternal(&mshrQueue,
blockAlign(pkt->getAddr()), blkSize,
- pkt, time, requestBus);
+ pkt, time, sched_send);
}
- MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
+ MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time)
{
// should only see clean evictions in a read-only cache
assert(!isReadOnly || pkt->cmd == MemCmd::CleanEvict);
assert(pkt->isWrite() && !pkt->isRead());
return allocateBufferInternal(&writeBuffer,
blockAlign(pkt->getAddr()), blkSize,
- pkt, time, requestBus);
+ pkt, time, true);
}
/**
@@ -571,26 +561,16 @@ class BaseCache : public MemObject
}
/**
- * Request the master bus for the given cause and time.
- * @param cause The reason for the request.
- * @param time The time to make the request.
- */
- void requestMemSideBus(RequestCause cause, Tick time)
- {
- memSidePort->requestBus(cause, time);
- }
-
- /**
- * Clear the master bus request for the given cause.
- * @param cause The request reason to clear.
+ * Schedule a send event for the memory-side port. If already
+ * scheduled, this may reschedule the event at an earlier
+ * time. When the specified time is reached, the port is free to
+ * send either a response, a request, or a prefetch request.
+ *
+ * @param time The time when to attempt sending a packet.
*/
- void deassertMemSideBusRequest(RequestCause cause)
+ void schedMemSideSendEvent(Tick time)
{
- // Obsolete... we no longer signal bus requests explicitly so
- // we can't deassert them. Leaving this in as a no-op since
- // the prefetcher calls it to indicate that it no longer wants
- // to request a prefetch, and someday that might be
- // interesting again.
+ memSidePort->schedSendEvent(time);
}
virtual bool inCache(Addr addr, bool is_secure) const = 0;