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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:43 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:43 -0400 |
| commit | b93c912013cd7f5417b92eaa33010af70e97f8ec (patch) | |
| tree | e381afa1a581e3d676e9c91d9999c490fa6b1a23 /src/mem/cache/base.hh | |
| parent | 71856cfbbcac94997839ac7831b3ac4b2ddf29a2 (diff) | |
| download | gem5-b93c912013cd7f5417b92eaa33010af70e97f8ec.tar.xz | |
mem: Remove redundant is_top_level cache parameter
This patch takes the final step in removing the is_top_level parameter
from the cache. With the recent changes to read requests and write
invalidations, the parameter is no longer needed, and consequently
removed.
This also means that asymmetric cache hierarchies are now fully
supported (and we are actually using them already with L1 caches, but
no table-walker caches, connected to a shared L2).
Diffstat (limited to 'src/mem/cache/base.hh')
| -rw-r--r-- | src/mem/cache/base.hh | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index d2cb11f33..6c87fad12 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -304,11 +304,6 @@ class BaseCache : public MemObject /** Do we forward snoops from mem side port through to cpu side port? */ const bool forwardSnoops; - /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should - * never try to forward ownership and similar optimizations to the cpu - * side */ - const bool isTopLevel; - /** * Is this cache read only, for example the instruction cache, or * table-walker cache. A cache that is read only should never see |