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author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:39 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:14:39 -0400 |
commit | 893533a1264bb369b47f74493adf30ce22829f34 (patch) | |
tree | 07c750519f5ac1b972be47a0ca6f68ee517d9f07 /src/mem/cache/base.hh | |
parent | a262908acc0a641700a03fcea89c48133f0467cd (diff) | |
download | gem5-893533a1264bb369b47f74493adf30ce22829f34.tar.xz |
mem: Allow read-only caches and check compliance
This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.
A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.
Diffstat (limited to 'src/mem/cache/base.hh')
-rw-r--r-- | src/mem/cache/base.hh | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index aaf0ea691..d2cb11f33 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -310,6 +310,14 @@ class BaseCache : public MemObject const bool isTopLevel; /** + * Is this cache read only, for example the instruction cache, or + * table-walker cache. A cache that is read only should never see + * any writes, and should never get any dirty data (and hence + * never have to do any writebacks). + */ + const bool isReadOnly; + + /** * Bit vector of the blocking reasons for the access path. * @sa #BlockedCause */ @@ -516,6 +524,8 @@ class BaseCache : public MemObject MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) { + // should only see clean evictions in a read-only cache + assert(!isReadOnly || pkt->cmd == MemCmd::CleanEvict); assert(pkt->isWrite() && !pkt->isRead()); return allocateBufferInternal(&writeBuffer, blockAlign(pkt->getAddr()), blkSize, |