Mem: Use cycles to express cache-related latencies

This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.

The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.

As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.

1 files changed, 5 insertions, 5 deletions

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index da72667b3..2e31836c0 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -229,7 +229,7 @@ class BaseCache : public MemObject
     /**
      * The latency of a hit in this device.
      */
-    const Tick hitLatency;
+    const Cycles hitLatency;
 
     /**
      * The latency of sending reponse to its upper level cache/core on a
@@ -237,7 +237,7 @@ class BaseCache : public MemObject
      * miss is much quicker that the hit latency. The responseLatency parameter
      * tries to capture this latency.
      */
-    const Tick responseLatency;
+    const Cycles responseLatency;
 
     /** The number of targets for each MSHR. */
     const int numTarget;
@@ -260,7 +260,7 @@ class BaseCache : public MemObject
     uint64_t order;
 
     /** Stores time the cache blocked for statistics. */
-    Tick blockedCycle;
+    Cycles blockedCycle;
 
     /** Pointer to the MSHR that has no targets. */
     MSHR *noTargetMSHR;
@@ -492,7 +492,7 @@ class BaseCache : public MemObject
         uint8_t flag = 1 << cause;
         if (blocked == 0) {
             blocked_causes[cause]++;
-            blockedCycle = curTick();
+            blockedCycle = curCycle();
             cpuSidePort->setBlocked();
         }
         blocked |= flag;
@@ -512,7 +512,7 @@ class BaseCache : public MemObject
         blocked &= ~flag;
         DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
         if (blocked == 0) {
-            blocked_cycles[cause] += curTick() - blockedCycle;
+            blocked_cycles[cause] += curCycle() - blockedCycle;
             cpuSidePort->clearBlocked();
         }
     }