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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 04:00:37 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 04:00:37 -0500 |
| commit | 987de4f5ccc5639ca03cc3c90e48bc06b5429823 (patch) | |
| tree | 1cb802979c420ae38c0471ba646097f163c407dd /src/mem/cache/base.hh | |
| parent | f26a28929583f2ed7fb55521e49c3f9bef557c05 (diff) | |
| download | gem5-987de4f5ccc5639ca03cc3c90e48bc06b5429823.tar.xz | |
mem: Tidy up the cache debug messages
Avoid redundant inclusion of the name in the DPRINTF string.
Diffstat (limited to 'src/mem/cache/base.hh')
| -rw-r--r-- | src/mem/cache/base.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index bda3df34a..cd2f55246 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -129,7 +129,8 @@ class BaseCache : public MemObject */ void requestBus(RequestCause cause, Tick time) { - DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); + DPRINTF(CachePort, "Scheduling request at %llu due to %d\n", + time, cause); reqQueue.schedSendEvent(time); } |