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authorCurtis Dunham <Curtis.Dunham@arm.com>2014-06-27 12:29:00 -0500
committerCurtis Dunham <Curtis.Dunham@arm.com>2014-06-27 12:29:00 -0500
commitf6f63ec0aa68f631691d9eccc18739722a0a9f17 (patch)
tree6d3cd4d0f43381980412ade2ed8266e3d3ba472d /src/mem/cache/base.hh
parent3be4f4b846f991c98fe1909631996c5b58d52437 (diff)
downloadgem5-f6f63ec0aa68f631691d9eccc18739722a0a9f17.tar.xz
mem: write streaming support via WriteInvalidate promotion
Support full-block writes directly rather than requiring RMW: * a cache line is allocated in the cache upon receipt of a WriteInvalidateReq, not the WriteInvalidateResp. * only top-level caches allocate the line; the others just pass the request along and invalidate as necessary. * to close a timing window between the *Req and the *Resp, a new metadata bit tracks whether another cache has read a copy of the new line before the writeback to memory.
Diffstat (limited to 'src/mem/cache/base.hh')
-rw-r--r--src/mem/cache/base.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 1567aaa62..297b80180 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -94,6 +94,7 @@ class BaseCache : public MemObject
Blocked_NoMSHRs = MSHRQueue_MSHRs,
Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
Blocked_NoTargets,
+ Blocked_PendingWriteInvalidate,
NUM_BLOCKED_CAUSES
};
@@ -168,6 +169,8 @@ class BaseCache : public MemObject
/** Return to normal operation and accept new requests. */
void clearBlocked();
+ bool isBlocked() const { return blocked; }
+
protected:
CacheSlavePort(const std::string &_name, BaseCache *_cache,