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| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
| commit | fbdeb6031664d71e19a25f51b6ee882d803dac30 (patch) | |
| tree | 0a3fa9a980e9b9a1013b3aff37080b045192b650 /src/mem/cache/base.hh | |
| parent | bead7f249a71f8b15ae92b0df9822abb52ca7323 (diff) | |
| download | gem5-fbdeb6031664d71e19a25f51b6ee882d803dac30.tar.xz | |
mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.
The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
Diffstat (limited to 'src/mem/cache/base.hh')
| -rw-r--r-- | src/mem/cache/base.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 8cd932f01..1f1f1469f 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -302,7 +302,7 @@ class BaseCache : public MemObject const int numTarget; /** Do we forward snoops from mem side port through to cpu side port? */ - const bool forwardSnoops; + bool forwardSnoops; /** * Is this cache read only, for example the instruction cache, or |