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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:18 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-09 14:40:18 -0400 |
| commit | 71aca6d29e686ecdec2828c8be1989f74d9b28d3 (patch) | |
| tree | 1ff5b36c08f5e1c3853208674608d141e2924c57 /src/mem/cache/base.hh | |
| parent | 7c4dc4491a6367888154129d2799b5f564ecb0d9 (diff) | |
| download | gem5-71aca6d29e686ecdec2828c8be1989f74d9b28d3.tar.xz | |
cache: coherence protocol enhancements & bug fixes
Allow lower-level caches (e.g., L2 or L3) to pass exclusive
copies to higher levels (e.g., L1). This eliminates a lot
of unnecessary upgrade transactions on read-write sequences
to non-shared data.
Also some cleanup of MSHR coherence handling and multiple
bug fixes.
Diffstat (limited to 'src/mem/cache/base.hh')
| -rw-r--r-- | src/mem/cache/base.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 2f1088609..94cdc959c 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -170,11 +170,11 @@ class BaseCache : public MemObject return mshr; } - void markInServiceInternal(MSHR *mshr) + void markInServiceInternal(MSHR *mshr, PacketPtr pkt) { MSHRQueue *mq = mshr->queue; bool wasFull = mq->isFull(); - mq->markInService(mshr); + mq->markInService(mshr, pkt); if (wasFull && !mq->isFull()) { clearBlocked((BlockedCause)mq->index); } |