summaryrefslogtreecommitdiff
path: root/src/mem/cache/base.hh
diff options
context:
space:
mode:
authorJavier Bueno <javier.bueno@metempsy.com>2018-11-09 16:02:04 +0100
committerJavier Bueno Hedo <javier.bueno@metempsy.com>2018-11-14 14:19:05 +0000
commit8590243fef2e4ccaefde3af767496dec44c6eb33 (patch)
tree6cf26aa22f26864a116bfe33ab0069ddb7084906 /src/mem/cache/base.hh
parente8e92a12af8cc499659ad840c84c99e293ff1e96 (diff)
downloadgem5-8590243fef2e4ccaefde3af767496dec44c6eb33.tar.xz
mem-cache: implement a probe-based interface
The HW Prefetcher of a cache can now listen events from their associated CPUs and from its own cache. Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3 Reviewed-on: https://gem5-review.googlesource.com/c/14155 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/mem/cache/base.hh')
-rw-r--r--src/mem/cache/base.hh22
1 files changed, 17 insertions, 5 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 52b0fdbcd..ad5ff3bc4 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -75,6 +75,7 @@
#include "mem/request.hh"
#include "params/WriteAllocator.hh"
#include "sim/eventq.hh"
+#include "sim/probe/probe.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
@@ -324,10 +325,11 @@ class BaseCache : public MemObject
/** Prefetcher */
BasePrefetcher *prefetcher;
- /**
- * Notify the prefetcher on every access, not just misses.
- */
- const bool prefetchOnAccess;
+ /** To probe when a cache hit occurs */
+ ProbePointArg<PacketPtr> *ppHit;
+
+ /** To probe when a cache miss occurs */
+ ProbePointArg<PacketPtr> *ppMiss;
/**
* The writeAllocator drive optimizations for streaming writes.
@@ -989,6 +991,9 @@ class BaseCache : public MemObject
*/
void regStats() override;
+ /** Registers probes. */
+ void regProbePoints() override;
+
public:
BaseCache(const BaseCacheParams *p, unsigned blk_size);
~BaseCache();
@@ -1136,6 +1141,14 @@ class BaseCache : public MemObject
}
/**
+ * Checks if the cache is coalescing writes
+ *
+ * @return True if the cache is coalescing writes
+ */
+ bool coalesce() const;
+
+
+ /**
* Cache block visitor that writes back dirty cache blocks using
* functional writes.
*/
@@ -1175,7 +1188,6 @@ class BaseCache : public MemObject
*/
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
-
};
/**