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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-09 09:59:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-09 09:59:25 -0500 |
| commit | eaa994e7f6c12f6dc3e17836052f76a5ce9bdc01 (patch) | |
| tree | d24450f54631a6e82b3c01b93fcf9e698eeee708 /src/mem/cache/base.hh | |
| parent | cda4c2d280e9c1becf3b4d0b6b384f63641c45ba (diff) | |
| download | gem5-eaa994e7f6c12f6dc3e17836052f76a5ce9bdc01.tar.xz | |
cache: Allow main memory to be at disjoint address ranges.
Diffstat (limited to 'src/mem/cache/base.hh')
| -rw-r--r-- | src/mem/cache/base.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index e522bc0c9..2a79fb354 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -269,7 +269,7 @@ class BaseCache : public MemObject /** * The address range to which the cache responds on the CPU side. * Normally this is all possible memory addresses. */ - Range<Addr> addrRange; + AddrRangeList addrRanges; public: /** System we are currently operating in. */ @@ -439,7 +439,7 @@ class BaseCache : public MemObject Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } - const Range<Addr> &getAddrRange() const { return addrRange; } + const AddrRangeList &getAddrRanges() const { return addrRanges; } MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) { |