Timing cache works for hello world test.

Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))

src/cpu/simple/timing.cc:
    Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
    Handle marking MSHR's in service
    Add support for getting CSHR's
src/mem/cache/base_cache.hh:
    Make these functions visible at the base cache level
src/mem/cache/cache.hh:
    make the functions virtual
src/mem/cache/cache_impl.hh:
    Rename the function to make sense
src/mem/packet.hh:
    Accidentally clearing the needsResponse field when sending a response back.

--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2

1 files changed, 8 insertions, 2 deletions

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 15a21efa1..4fbda4074 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -118,9 +118,15 @@ BaseCache::CacheEvent::process()
     {
         if (!cachePort->isCpuSide)
             pkt = cachePort->cache->getPacket();
-        //Else get coherence req
+        else
+            pkt = cachePort->cache->getCoherencePacket();
+        bool success = cachePort->sendTiming(pkt);
+        cachePort->cache->sendResult(pkt, success);
+        return;
     }
-    cachePort->sendTiming(pkt);
+    //Know the packet to send, no need to mark in service (must succed)
+    bool success = cachePort->sendTiming(pkt);
+    assert(success);
 }
 
 const char *