Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus

into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 7b7a1b03ffed36bce49595962ea57c08d1d1a4ad

1 files changed, 2 insertions, 0 deletions

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 0141fa2a0..4df13fb2b 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -221,6 +221,7 @@ BaseCache::CacheEvent::process()
         }
         else if (!cachePort->isCpuSide)
         {
+            assert(cachePort->cache->doMasterRequest());
             //MSHR
             pkt = cachePort->cache->getPacket();
             MSHR* mshr = (MSHR*) pkt->senderState;
@@ -238,6 +239,7 @@ BaseCache::CacheEvent::process()
         }
         else
         {
+            assert(cachePort->cache->doSlaveRequest());
             //CSHR
             pkt = cachePort->cache->getCoherencePacket();
             bool success = cachePort->sendTiming(pkt);