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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-10 17:32:24 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-10 17:32:24 -0400 |
commit | 27c59dc370f2f851a8426d6024fa4d2acb296238 (patch) | |
tree | 9373e4e7feae294fdbd593c083719f89ae326b64 /src/mem/cache/base_cache.cc | |
parent | 549412b33361629b03d9d85dac3bb3efa2f07baf (diff) | |
parent | aff3d92c007f7c971eed8417b1d7602394755398 (diff) | |
download | gem5-27c59dc370f2f851a8426d6024fa4d2acb296238.tar.xz |
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision : 7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r-- | src/mem/cache/base_cache.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 0141fa2a0..4df13fb2b 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -221,6 +221,7 @@ BaseCache::CacheEvent::process() } else if (!cachePort->isCpuSide) { + assert(cachePort->cache->doMasterRequest()); //MSHR pkt = cachePort->cache->getPacket(); MSHR* mshr = (MSHR*) pkt->senderState; @@ -238,6 +239,7 @@ BaseCache::CacheEvent::process() } else { + assert(cachePort->cache->doSlaveRequest()); //CSHR pkt = cachePort->cache->getCoherencePacket(); bool success = cachePort->sendTiming(pkt); |