Now timing reads work in single level of cache with simple cpu

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
    Changes to handle timing reads in Simple CPU (blocking buffers)

--HG--
extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f

1 files changed, 31 insertions, 0 deletions

diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index aaaf1bdef..15a21efa1 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -98,6 +98,37 @@ BaseCache::CachePort::clearBlocked()
     blocked = false;
 }
 
+BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
+    : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
+{
+    this->setFlags(AutoDelete);
+    pkt = NULL;
+}
+
+BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
+    : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
+{
+    this->setFlags(AutoDelete);
+}
+
+void
+BaseCache::CacheEvent::process()
+{
+    if (!pkt)
+    {
+        if (!cachePort->isCpuSide)
+            pkt = cachePort->cache->getPacket();
+        //Else get coherence req
+    }
+    cachePort->sendTiming(pkt);
+}
+
+const char *
+BaseCache::CacheEvent::description()
+{
+    return "timing event\n";
+}
+
 Port*
 BaseCache::getPort(const std::string &if_name, int idx)
 {