summaryrefslogtreecommitdiff
path: root/src/mem/cache/base_cache.cc
diff options
context:
space:
mode:
authorRon Dreslinski <rdreslin@umich.edu>2006-10-09 16:37:02 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-09 16:37:02 -0400
commitafce51d10ad1441247b39edb2a61b85d3cd7af04 (patch)
tree43e7ee9339ec3dfb49cf334fba45208a8ea74616 /src/mem/cache/base_cache.cc
parentbc732b59fd82689490306090974f1f4c06741b0a (diff)
downloadgem5-afce51d10ad1441247b39edb2a61b85d3cd7af04.tar.xz
Set size properly on uncache accesses
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.hh: Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct --HG-- extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r--src/mem/cache/base_cache.cc16
1 files changed, 12 insertions, 4 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 6b035bc16..1a0f63d17 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -109,10 +109,11 @@ BaseCache::CachePort::recvRetry()
if (!isCpuSide)
{
pkt = cache->getPacket();
+ MSHR* mshr = (MSHR*)pkt->senderState;
bool success = sendTiming(pkt);
DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
pkt->getAddr(), success ? "succesful" : "unsuccesful");
- cache->sendResult(pkt, success);
+ cache->sendResult(pkt, mshr, success);
if (success && cache->doMasterRequest())
{
//Still more to issue, rerequest in 1 cycle
@@ -123,7 +124,9 @@ BaseCache::CachePort::recvRetry()
}
else
{
- pkt = cache->getCoherencePacket();
+ //pkt = cache->getCoherencePacket();
+ //We save the packet, no reordering on CSHRS
+ pkt = cshrRetry;
bool success = sendTiming(pkt);
if (success && cache->doSlaveRequest())
{
@@ -182,10 +185,11 @@ BaseCache::CacheEvent::process()
{
//MSHR
pkt = cachePort->cache->getPacket();
+ MSHR* mshr = (MSHR*) pkt->senderState;
bool success = cachePort->sendTiming(pkt);
DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
pkt->getAddr(), success ? "succesful" : "unsuccesful");
- cachePort->cache->sendResult(pkt, success);
+ cachePort->cache->sendResult(pkt, mshr, success);
if (success && cachePort->cache->doMasterRequest())
{
//Still more to issue, rerequest in 1 cycle
@@ -198,7 +202,11 @@ BaseCache::CacheEvent::process()
//CSHR
pkt = cachePort->cache->getCoherencePacket();
bool success = cachePort->sendTiming(pkt);
- if (success && cachePort->cache->doSlaveRequest())
+ if (!success) {
+ //Need to send on a retry
+ cachePort->cshrRetry = pkt;
+ }
+ else if (cachePort->cache->doSlaveRequest())
{
//Still more to issue, rerequest in 1 cycle
pkt = NULL;