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authorRon Dreslinski <rdreslin@umich.edu>2006-10-10 01:32:18 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-10 01:32:18 -0400
commitcc78d86661dfccaca2f144d5bdcc75761bf52521 (patch)
tree7ca24a540b6b175ac9a7117122c43a84d9e6b1da /src/mem/cache/base_cache.cc
parentec8a437b2c11453e9b94978b0c18a31f12ec04ac (diff)
downloadgem5-cc78d86661dfccaca2f144d5bdcc75761bf52521.tar.xz
Fix several bugs pertaining to upgrades/mem leaks.
src/mem/cache/base_cache.cc: Fix a bug about not having a request to send src/mem/cache/base_cache.hh: Fix a bug with the blocking code src/mem/cache/cache.hh: AFix a bug with snoop hits in WB buffer src/mem/cache/cache_impl.hh: Fix a bug with snoop hits in WB buffer Also, add better DPRINTF's src/mem/cache/miss/miss_queue.cc: Fix a bug with upgrades (Need to clean it up later) src/mem/cache/miss/mshr.cc: Fix a memory leak bug, still some outstanding with writebacks not being deleted src/mem/cache/miss/mshr_queue.cc: Fix a bug about upgrades (need to clean up later) src/mem/packet.hh: Fix for newly added cmd attribute for upgrades tests/configs/memtest.py: More interesting testcase --HG-- extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r--src/mem/cache/base_cache.cc15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 8e2f4d233..c4d42c0a4 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -104,10 +104,12 @@ BaseCache::CachePort::recvRetry()
if (result)
drainList.pop_front();
}
+ if (!result) return;
}
if (!isCpuSide)
{
+ if (!cache->doMasterRequest()) return;
pkt = cache->getPacket();
MSHR* mshr = (MSHR*)pkt->senderState;
bool success = sendTiming(pkt);
@@ -179,10 +181,23 @@ BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
void
BaseCache::CacheEvent::process()
{
+ if (!cachePort->drainList.empty()) {
+ //We have some responses to drain first
+ bool result = true;
+ while (result && !cachePort->drainList.empty()) {
+ result = cachePort->sendTiming(cachePort->drainList.front());
+ if (result)
+ cachePort->drainList.pop_front();
+ }
+ if (!result) return;
+ }
+
if (!pkt)
{
if (!cachePort->isCpuSide)
{
+ //For now, doMasterRequest somehow is still getting set
+ if (!cachePort->cache->doMasterRequest()) return;
//MSHR
pkt = cachePort->cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;