diff options
author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-19 21:26:46 -0400 |
---|---|---|
committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-19 21:26:46 -0400 |
commit | 780aa0a0ebb765781a31d0fb58257b1efb1f324a (patch) | |
tree | ae6dbaca9ea90d3fa7ed3b16c633229a7f995dd0 /src/mem/cache/base_cache.cc | |
parent | cc1feb9f6ddf9d0a58365ffa9f7ae948bf19901d (diff) | |
download | gem5-780aa0a0ebb765781a31d0fb58257b1efb1f324a.tar.xz |
Fix corner case on assertion.
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r-- | src/mem/cache/base_cache.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 936a9c1fa..e0301a757 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -132,7 +132,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt) pkt_data = pkt->getPtr<uint8_t>() + offset; write_data = target->getPtr<uint8_t>(); data_size = pkt->getSize() - offset; - assert(data_size > pkt->getSize()); + assert(data_size >= pkt->getSize()); if (data_size > target->getSize()) data_size = target->getSize(); } |